This invention relates to semiconductor devices and methods of manufacture and more particularly to semiconductor devices having improved insulation between interlevel conductive layers. In one aspect of the invention, the insulator thickness formed on the edge of an electrode is enhanced to improve the insulation between that electrode and a laterally spaced conductive region.
Semiconductor devices are widely used throughout the electronics industry and application of semiconductor devices has dramatically increased in other industries such as games, automotive applications, industrial controls, etc. One of the major reasons for increased application of semiconductor devices is directly attributable to the dramatic reduction in production costs achieved by the electronics industry during recent years. This is vividly illustrated in application of semiconductor devices to the computer industry where there has been a demand for more and more storage capacity in the form of high density, low cost memories. For example, in the past 10 years semiconductor memories have been developed where the number of bits of storage per semiconductor chip has increased from 16 to 64 K. At the same time, the cost per bit has been reduced by a factor of approximately 200. By increasing the density of semiconductor elements on a single chip, the manufacturing costs can be dramatically decreased. To illustrate, the production cost of a semiconductor memory lies primarily in the bonding, packaging, testing and handling operations, rather than in the cost of the silicon chip which contains the actual circuitry. As a result, any circuit which can be contained within a given chip size; for example, 30,000 square mils, will cost about the same as any other. Thereby by forming large numbers of memory cells in a single chip, large economies in the cost per bit can result, assuming reasonable yields can be obtained. However, as the density and complexity of the chip increases, the yield decreases, offsetting some of the advantage otherwise obtainable from high packing density.
Recognizing the tremendous cost reduction potential that can be achieved by increasing density of semiconductor devices formed on a single chip, the electronics industry has focused a great deal of attention toward the design and manufacture of integrated circuits characterized by extremely high density complex circuitry. Such circuits are commonly referred to as very large scale integration devices (VLSI). The progress of the electronics industry in increasing density of semiconductor devices is evident in viewing the progression of dynamic random access memories from a storage capability of 4 K bits typically available in 1975 to 64 K bits announced by several companies in 1979. The size of the 64 K bit chip is normally the same size as the 4 K chip.
As device geometries have become smaller to accommodate .the higher packing density, several problems have become manifest. These problems significantly reduce yields and offset the cost savings achieved by higher packing density. One of the most difficult problems encountered in manufacturing small geometry devices relates to interlevel shorts. This has been a particularly difficult problem in the manufacture of VLSI metal insulator semiconductor devices where the gate insulator is of a thickness much less than 1000 angstroms--for example, on the order of 200 angstroms or less. Hereinafter this category of integrated circuits will be referred to generally as MOS devices, and is intended to include the various types of such devices, both N-channel and P-channel, metal gate, silicon gate, silicon oxide gate insulator and other gate insulator devices known in the art, and related devices structures, such as CCD (charge coupled devices) and CID (charge injection devices). In such MOS devices, a common failure mode is for a doped region in the substrate, such as the source or drain region of an MOS transistor, to short through the thin insulating layer to the gate or control electrode. A related type problem in such devices relates to shorts between laterally spaced conductors formed on the surface of a substrate. This latter problem is common in devices requiring double-level conductors. Such conductors conventionally may be polycrystalline silicon. Devices of this type are described in the following pending patent applications, all assigned to Texas Instruments: Ser. No. 648,594, filed Jan. 12, 1976 by Clinton Kuo; Ser. No. 722,841, filed Sep. 13, 1976 by Clinton Kuo; Ser. No. 754,144, filed Dec. 27, 1976 by L. S. Wall; and Ser. No. 762,613, filed Jan. 26, 1977 by D. J. MacElroy. In addition, a double-level polysilicon structure is shown in Electronics, Feb. 19, 1976, at pages 116-121.
In forming devices such as described in the aforementioned prior art applications, conventional semiconductor processing does not permit forming a sufficient thickness of insulation between the two levels of polysilicon conductors. As will be described in more detail below, the interlevel insulator thickness between the two levels of polysilicon conductors is typically limited to about 1.4 times the gate oxide thickness of the MOS device. For VLSI applications, this restriction is particularly severe since the gate insulator may be on the order of 200 angstroms or less, and the resulting insulation layer of about 280 angstroms laterally separating two conductors is subject to a high failure rate and is characterized by unacceptably low breakdown voltage limitations.
Another problem that has become manifest, particularly in MOS VLSI-type structures is excessive overlap of the gate electrode over source and drain regions. Even though it is typical in conventional processing to use self-aligned structures, there is significant lateral diffusion or scattering (during ion implant) of the impurities used to form the source and drain regions of an MOS transistor under the gate region of the device. For example, even if the source and drain regions are formed by ion implantation, it is not uncommon for there to be a lateral scattering of the ions by as much as 1000 angstroms. This reduces the effective gate length and increases the capacitance of the device thereby decreasing the speed of operation. These problems become more critical when extremely small geometry devices are being manufactured.
A further problem that has been encountered in conventional processes used to manufacture small geometry or VLSI type devices relates to contamination formed at the edges of the gate electrodes in MOS devices. Such contamination adversely affects device performance and significantly decreases yield.
An additional problem encountered, particularly in MOS type devices has been referred to in the art as "birds beaking". This refers to a MOS structure where the gate oxide thickness at the edges of a gate electrode increases during manufacturing steps involving oxidations which are performed subsequent to formation of the gate and gate oxide. This results in a non-uniform gate oxide thickness underneath the gate and adversely affects device operation. This "birds beaking" problem is particularly acute in devices requiring double level polysilicon structures.
As can be appreciated by those skilled in the art, these above described problems all adversely affect yield and increase manufacturing costs of semiconductor devices.
It is therefore a principle object of the present invention to provide an improved semiconductor structure characterized by fewer interlevel conductor shorts by enhancing the insulator thickness on the edges of electrodes. It is a further object of the invention to provide an improved MOS semiconductor device having reduced gate overlap. A further object of the invention is to provide an MOS structure having a gate electrode, the edges of which are protected from contamination in manufacturing steps subsequent to formation of the gate. An additional object of the invention is to provide an MOS structure having a more uniform gate oxide thickness along the channel from the source to the drain the thickness of which is not significantly affected by subsequent processing.